The present invention generally relates to semiconductor devices and production methods thereof, and more particularly to a semiconductor device having first and second transistors and a production method thereof, where there are three demands on the first and second transistors. First, there is a demand to suppress generation of crystal defects in the first transistor by not subjecting an impurity diffusion layer of the first transistor to an etching. Second, there is a demand to form a conductor layer on the first transistor via an insulator layer. Third, there is a demand to obtain a satisfactory current driving capability for the second transistor.
For example, in a dynamic random access memory (DRAM) which is provided with stacked capacitors, there are demands to simultaneously satisfy the above three conditions in order to improve the charge storage characteristic of memory cells. A first condition is not to subject an impurity diffusion layer of a transistor which makes up the memory cell so as to suppress the generation of crystal defects. A second condition is to facilitate the formation of a storage electrode by flattening a layer below the storage electrode. A third condition is to ensure a satisfactory current driving capability of the transistor of a peripheral circuit.
Conventionally, there is a DRAM provided with stacked capacitors as shown in FIG. 1K which shows a cross section of an essential part of this conventional DRAM. The DRAM includes a p-type silicon (Si) substrate 1, a field oxide layer 2 which forms a device isolation region, a memory cell 3, and a peripheral circuit 4.
The memory cell 3 is made up of an n-channel insulated-gate type field effect transistor (hereinafter simply referred to as an nMOS FET) 5 which forms a transistor for controlling input/output of charge, and a stacked capacitor 6. The nMOS FET 5 has a lightly doped drain (LDD) structure. A source diffusion layer 7 of the nMOS FET 5 is made up of an n.sup.- -type source diffusion layer 8 and an n.sup.+ -type source diffusion layer 9. A drain diffusion layer 10 of the nMOS FET 5 is made up of an n.sup.- -type drain diffusion layer 11 and an n.sup.+ -type drain diffusion layer 12.
A gate insulator layer 13 is made of silicon dioxide (SiO.sub.2), a gate electrode (word line) 14 is made of polysilicon, an interlayer insulator 15 is made of SiO.sub.2, an interlayer insulator 16 is made of phospho-silicate glass (PSG), and a bit line 17 is made of aluminum (Al). The bit line 17 makes an ohmic contact with the n.sup.+ -type source diffusion layer 9 via a contact hole 18.
The stacked capacitor 6 is made up of a stacked structure including a polysilicon storage electrode 19, a SiO.sub.2 capacitor insulator layer 20 and a polysilicon confronting electrode 21. The storage electrode 19 makes an ohmic contact with the n.sup.+ -type drain diffusion layer 12 via a contact hole 22.
The peripheral circuit 4 is made up of an nMOS FET 23 which also has the LDD structure. A source diffusion layer 24 of the nMOS FET 23 is made up of an n.sup.- -type source diffusion layer 25 and an n.sup.+ -type source diffusion layer 26. On the other hand, a drain diffusion layer 27 of the nMOS FET 23 is made up of an n.sup.- -type drain diffusion layer 28 and an n.sup.+ -type drain diffusion layer 29.
A gate insulator layer 30 is made of SiO.sub.2, a gate electrode 31 is made of polysilicon, and an interconnection 32 is made of Al. The interconnection 32 makes an ohmic contact with the n.sup.+ -type drain diffusion layer 29 via a contact hole 33.
In addition, the bit line 17 makes an ohmic contact with the n.sup.+ -type source diffusion layer 26 via a contact hole 34.
This conventional DRAM is produced in a sequence shown in FIGS. 1A through 1K.
First, the p-type Si substrate 1 is prepared as shown in FIG. 1A. A surface of this p-type Si substrate 1 is selectively oxidized to form the field oxide layer 2 which has a thickness of 5000 .ANG., for example. Then, the SiO.sub.2 layers 13 and 30 are formed in a device region by a thermal oxidation to a thickness of 150 .ANG., for example. Furthermore, a polysilicon layer 35 having a thickness of 2000 .ANG., for example, is formed on the entire surface of the stacked structure by a chemical vapor deposition (CVD).
Next, the polysilicon layer 35 is patterned, and as shown in FIG. 1B, the gate electrodes 14 and 31 are formed. Then, the gate electrodes 14 and 31 and the field oxide layer 2 are used as a mask when implanting phosphorous (P) ions into the p-type Si substrate 1 with an energy of 50 keV and a dosage of 1.times.10.sup.13 cm.sup.-2, for example. As a result, n.sup.- -type diffusion layers 36 and 37 are formed.
Thereafter, as shown in FIG. 1C, a SiO.sub.2 layer 40 having a thickness of 3000 .ANG., for example, is formed on the entire surface of the stacked structure by a CVD. A reactive ion etching (RIE) is made with respect to the SiO.sub.2 layer 40 and the SiO.sub.2 layers 13 and 30 under the SiO.sub.2 layer 40, so as to partially expose the n.sup.- -type diffusion layers 36, 37, 38 and 39 as shown in FIG. 1D. In this state, so-called side wall SiO.sub.2 layers 41, 42, 43 and 44 are formed on the side wall portions of the gate electrodes 14 and 31.
Next, a thermal oxidation is made to form a SiO.sub.2 layer 45 which has a thickness of 150 .ANG., for example, on the exposed surfaces of the p-type Si substrate 1 and the gate electrodes 14 and 31 as shown in FIG. 1E. Thereafter, the gate electrodes 14 and 31, the side wall SiO.sub.2 layers 41, 42, 43 and 44 and the field oxide layer 2 are used as a mask when implanting arsenide (As) ions into the p-type Si substrate 1 with an energy of 50 keV and a dosage of 4.times.10.sup.15 cm.sup.-2, for example. As a result, the nMOS FET 5 and the nMOS FET 23 are formed. The nMOS FET 5 has the source diffusion layer 7 which is made up of the n.sup.- -type source diffusion layer 8 and the n.sup.+ -type source diffusion layer 9, and the drain diffusion layer 10 which is made up of the n.sup.- -type drain diffusion layer 11 and the n.sup.+ -type drain diffusion layer 12. Similarly, the nMOS FET 23 has the source diffusion layer 24 which is made up of the n.sup.- -type source diffusion layer 25 and the n.sup.+ -type source diffusion layer 26, and the drain diffusion layer 27 which is made up of the n.sup.- -type drain diffusion layer 28 and the n.sup.+ -type drain diffusion layer 29.
Then, as shown in FIG. 1F, a SiO.sub.2 layer having a thickness of 1000 .ANG., for example, is formed on the entire surface of the stacked structure by a CVD so as to form the interlayer insulator 15 which is made of SiO.sub.2. The contact hole 22 which has a width of 0.8 .mu.m, for example, is formed in the interlayer insulator 15 above the n.sup.+ -type drain diffusion layer 12.
Next, as shown in FIG. 1G, a polysilicon layer 46 having a thickness of 2000 .ANG., for example, is formed on the entire surface of the stacked structure. As ions are implanted into this polysilicon layer 46 with an energy of 50 keV and a dosage of 1.times.10.sup.15 cm.sup.-2, for example, so as to reduce the resistance. The polysilicon layer 46 is then patterned as shown in FIG. 1H, and the storage electrode 19 which makes an ohmic contact with the n.sup.+ -type drain diffusion layer 12 via the contact hole 22 is formed.
Thereafter, an oxide layer which is naturally formed on the exposed surface of the storage electrode 19 is removed by an etching using a hydrogen fluoride (HF) solution. Further, a thermal oxidation is carried out to form a SiO.sub.2 capacitor insulator layer 20 which has a thickness of 100 .ANG., for example, on the exposed surface of the storage electrode 19 as shown in FIG. 1I.
Next, a polysilicon layer 47 having a thickness of 2000 .ANG., for example, is formed on the entire surface of the stacked structure as shown in FIG. 1J, and P is thermally diffused into the polysilicon layer 47 to reduce the resistance. Thereafter, this polysilicon layer 47 is patterned to form the confronting electrode 21 as shown in FIG. 1K.
Then, the PSG layer 16 is formed on the entire surface of the stacked structure to a thickness of 5000 .ANG., for example, as shown in FIG. 1K. The contact holes 18, 33 and 34 are formed in the PSG layer 16, and the bit line 17 and the other interconnection 32 are formed. As a result, the conventional DRAM having the stacked capacitor 6 is obtained.
According to the conventional method of producing the DRAM shown in FIG. 1K, the side wall SiO.sub.2 layers 41 and 42 are formed on the side wall portions of the gate electrode 14 as shown in FIG. 1D in order to realize the LDD structure of the nMOS FETs 5 and 23. The side wall SiO.sub.2 layers 41 and 42 flatten the vertical stepped portions at the side wall portions of the gate electrode 14, and have a function of facilitating the formation of the storage electrode 19.
FIGS. 2A through 2C are cross sectional views and FIG. 3 is a plan view for explaining the side wall SiO.sub.2 layers 41 and 42. For the sake of convenience, a consideration will be given of a case where the storage electrode 19 is formed without forming the side wall SiO.sub.2 layers 41 and 42 at the side wall portions of the gate electrode 14.
In this case, a SiO.sub.2 layer 48 which covers the gate electrode 14 and the n.sup.- -type diffusion layers 36 and 37 are first formed as shown in FIG. 2A. After forming a contact hole 49 in the SiO.sub.2 layer 48, the polysilicon layer 46 is formed on the entire surface of the stacked structure. Then, after the resistance of this polysilicon layer 46 is reduced by carrying out an ion implantation with respect to the polysilicon layer 46, an RIE is carried out and the polysilicon layer 46 is patterned to form the storage electrode 19 as shown in FIG. 2B.
However, side wall portions 48A and 48B of the SiO.sub.2 layer 48 along the gate electrode 14 are formed vertically in accordance with the shape of the side wall portions of the gate electrode 14. For this reason, when the polysilicon layer 46 is etched by the RIE and the storage electrode 19 is formed as shown in FIG. 2B, polysilicon 50 and 51 remain at the side wall portions 48A and 48B of the SiO.sub.2 layer 48 as shown in FIGS. 2C and 3. For example, there is a problem in that the polysilicon 50 may extend across two mutually adjacent storage electrodes 19 and short-circuit these storage electrodes 19. On the other hand, there is a problem in that the polysilicon 51 may come off during a subsequent process and adhere across two mutually adjacent storage electrodes 19 and short-circuit these storage electrodes 9.
The side wall portions of the gate electrode 14 may be formed as overhangs. In this case, the side wall portions 48A and 48B of the SiO.sub.2 layer 48 are also formed as overhangs. For this reason, when the RIE is carried out with respect to the polysilicon layer 46 and the storage electrode 19 is formed, polysilicon inevitably remains at the side wall portions 48A and 48B. When the side wall portions of the gate electrode 14 are formed as overhangs, the above described problems become particularly notable.
Accordingly, in the conventional DRAM, the side wall SiO.sub.2 layers 41 and 42 are formed at the side wall portions of the gate electrode 14 as shown in FIG. 1D and the vertical stepped portions at the side wall portions of the gate electrode 14 are flattened so as to facilitate the formation of the storage electrode 19.
However, the conventional DRAM described above suffer from the following problems.
First, when forming the side wall SiO.sub.2 layers 41, 42, 43 and 44 by the RIE as shown in FIG. 1D, the surface of the n.sup.- -type diffusion layer 37 is subjected to the plasma atmosphere. As a result, there is a problem in that a crystal defect is generated at the surface of the n.sup.- -type diffusion layer 37 due to contamination of metals such as iron, copper and nickel which are included in the internal wall of a chamber containing the plasma or included in the plasma atmosphere caused by electrode erosion. Because the storage electrode 19 is connected to the surface of the n.sup.- -type diffusion layer 37, the charge storage characteristic (refresh characteristic) of the memory cell 3 is deteriorated by the crystal defect.
Hence, a description will be given of a conceivable method of producing the DRAM to eliminate the problem of the conventional method, by referring to FIG. 4. According to this conceivable method, when etching by the RIE the SiO.sub.2 layer 40 which is formed on the entire surface of the stacked structure in the step shown in FIG. 1C, the etching is ended halfway as shown in FIG. 4. Then, a SiO.sub.2 layer 52 having a predetermined thickness is formed, and side wall SiO.sub.2 layers 53, 54, 55 and 56 are formed at the side wall portions of the gate electrodes 14 and 31.
According to this conceivable method, it is possible to form the side wall SiO.sub.2 layers 53 and 54 at the side wall portions of the gate electrode 14 without subjecting the n.sup.- -type diffusion layer 37 to the plasma atmosphere. For this reason, it is possible to protect the n.sup.- -type diffusion layer 37 from metal contamination and easily form the storage electrode 19.
However, a problem occurs according to this conceivable method at a latter stage when the n.sup.+ -type source diffusion layer 9 and the n.sup.+ -type drain diffusion layer 12 of the nMOS FET 5 and the n.sup.+ -type source diffusion layer 26 and the n.sup.+ -type drain diffusion layer 29 of the nMOS FET 23 are formed as shown in FIG. 1E described above.
In other words, when forming the n.sup.+ -type source diffusion layer 9, the n.sup.+ -type drain diffusion layer 12, the n.sup.+ -type source diffusion layer 26 and the n.sup.+ -type drain diffusion layer 29 according to the conceivable method of FIG. 4, it is necessary to accelerate the As ion implantation into the p-type Si substrate 1 such that the As ions penetrate the SiO.sub.2 layer 52. But it is difficult to control the thickness of the SiO.sub.2 layer 52 with a high accuracy according to the RIE, and the As ions must be implanted with an energy which takes into consideration the thickness distribution of the SiO.sub.2 layer 52. Hence, when the As ion implantation is carried out under such consideration, the As ions penetrate the gate electrodes 14 and 31 and reach the channel region, thereby introducing undesirable effects on the characteristics of the nMOS FETs 5 and 23.
On the other hand, there is another problem in that the ion implantation with a high acceleration and a high dosage leads to a poor throughput.
Second, the conventional DRAM shown in FIG. 1K has the n.sup.+ -type drain diffusion layer 12 provided in the nMOS FET 5, but the As ion implantation with respect to the p-type Si substrate 1 must be carried out with a high dosage in order to form this n.sup.+ -type drain diffusion layer 12. In this case, the region which is subjected to the As ion implantation is transformed into an amorphous state, and it becomes necessary to thereafter carry out a thermal process to transform the region back into a crystal state. But when such a recrystallization is carried out, a dislocation loop is generated in the n.sup.+ -type drain diffusion layer 12 and there is a problem in that the charge storage characteristic of the memory cell 3 is deteriorated thereby.
In addition, in the conventional DRAM shown in FIG. 1K, the tip end of the side wall SiO.sub.2 layer 42 makes direct contact with the p-type Si substrate 1 as shown in FIG. 1D, and an angle the tip end of the side wall SiO.sub.2 layer 42 makes with respect to the surface of the p-type Si substrate 1 cannot be made small. As a result, there are problems in that a stress is concentrated at the tip end portion of the side wall SiO.sub.2 layer 42 and an edge dislocation is generated in the n.sup.- -type drain diffusion layer 11 or the n.sup.+ -type drain diffusion layer 12 about this portion when the n.sup.+ -type drain diffusion layer 12 is formed (recrystallization takes place), thereby deteriorating the charge storage characteristic of the memory cell 3.
The dislocation loop and the edge dislocation are also generated in the source diffusion layer 7. However, since the source diffusion layer 7 passes the charge, the dislocation loop and the edge dislocation in the source diffusion layer 7 essentially do not affect the charge storage characteristic of the memory cell 3.
The transistor which makes up the memory cell merely controls the input/output of the charge. Thus, virtually no problems are generated from the point of view of the operation characteristic of this transistor even when the resistances of the source diffusion layer and the drain diffusion layer thereof are large. Accordingly, it is sufficient to provide only the n.sup.- -type source diffusion layer and the n.sup.- -type drain diffusion layer with respect to the transistor which makes up the memory cell, and this in effect avoids the generation of the dislocation loop and the edge dislocation in the drain diffusion layer.
On the other hand, the current driving capability must be ensured for the transistor which makes up the peripheral circuit. For this reason, the resistances of the source diffusion layer and the drain diffusion layer of this transistor must be small. As a result, the n.sup.+ -type source diffusion layer and the n.sup.+ -type drain diffusion layer must be provided for the transistor which makes up the peripheral circuit.
Therefore, in the conventional DRAM, there is a demand to form the transistor which makes up the memory cell so that a source diffusion layer and a drain diffusion layer thereof are respectively made solely from an n.sup.- -type source diffusion layer and an n.sup.- -type drain diffusion layer, and to form the transistor which makes up the peripheral circuit so that a source diffusion layer includes an n.sup.- -type source diffusion layer and an n.sup.+ -type source diffusion layer and a drain diffusion layer includes an n.sup.- -type drain diffusion layer and an n.sup.+ -type drain diffusion layer.